1. Field of the Invention
The present invention relates to a method of automatically placing wires in semiconductor integrated circuits and the like.
2. Description of Related Art
For semiconductor integrated circuits and the like, the automatic placement of wires in circuits is executed. This automatic placement is performed with use of a CAD program or the like running on a processer. In these years, as integrated circuits become larger in scale, the time required for this automatic placement of wires is increasing. Accordingly, in Japanese Patent No. 2974398 (hereinafter called reference 1), it is described that a plurality of processers are used to perform the automatic placement of wires in parallel.
In the technique described in reference 1, a wiring area is divided into a plurality of small areas, and automatic routing is performed for each small area in parallel processing. In the technique described in reference 1, the plurality of small areas where wires are placed are combined into a plurality of medium areas. Then, automatic routing of wires is further performed for each medium area in parallel processing. These medium areas are again divided into small areas, which are combined into a plurality of new medium areas different from the previous medium areas. Then, automatic wire routing is performed for the new medium areas. According to the automatic wire routing method described in reference 1, the division into small areas and the combination into medium areas are repeated to place wires, and hence it is difficult to sufficiently shorten the time required for placing wires.
Further, shield wires to prevent cross-talk noise may be placed adjacent to signal wires. The shield wires are placed adjacent to ones of signal wires already placed, which are likely to be affected by cross-talk noise to cause a problem. If also for these shield wires the above routing is performed, the time required until wire placement is determined may further increase.
As devices become larger in scale, the time required for placing wires increases. Further, even if a device is divided into a plurality of areas and wire routing is performed for each area in parallel processing, it is difficult to sufficiently shorten the time required for placing wires.